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HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs
| Date | Stars |
|---|---|
| 2026-07-31 | 339 |
| 2026-08-01 | 339 |
| 2026-08-02 | 339 |
| 2026-08-06 | 339 |
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<th width="100%" colspan="6"><img src="https://www.xilinx.com/content/dam/xilinx/imgs/press/media-kits/corporate/xilinx-logo.png" width="30%"/><h1>CHaiDNN-v2</h2>
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<th rowspan="6" width="17%">Analysis and Eval</th>
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<td align="center" colspan="2"><a href="./docs/SUPPORTED_LAYERS.md">Supported Layers</a></td>
<td align="center" colspan="2"><a href="./docs/PERFORMANCE_SNAPSHOT.md">Performance/Resource Utilization</a></td>
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<td align="center" colspan="4"><a href="./docs/PERFORMANCE_EVAL.md">Performance Eval</a></td>
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<th rowspan="7" width="17%">Design and Development</th>
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<td align="center"><a href="./docs/API.md">API Reference</a></td>
<td align="center"><a href="./docs/QUANTIZATION.md">Quantization User Guide for CHaiDNN</a></td>
<td align="center"><a href="./docs/MODELZOO.md">Model Zoo</a></td>
<td align="center"><a href="./docs/RUN_NEW_NETWORK.md">Running Inference on new Network</a></td>
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<td align="center"><a href="./docs/BUILD_USING_SDX_GUI.md">Creating SDx GUI Project</a></td>
<td align="center"><a href="./docs/CONFIGURABLE_PARAMS.md">Configurable Parameters</a></td>
<td align="center"><a href="./docs/CUSTOM_PLATFORM_GEN.md">Custom Platform Generation</a></td>
<td align="center"><a href="./docs/SOFTWARE_LAYER_PLUGIN.md">Software Layer Plugin</a></td>
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<td align="center" colspan="2"><a href="https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1027-sdsoc-user-guide.pdf">SDSoC Environment User Guide</a></td>
<td align="center" colspan="2"><a href="./docs/HW_SW_PARTITIONING.md">Hardware-Software Partitioning for Performance</a></td>
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## Introduction
CHaiDNN is a Xilinx Deep Neural Network library for acceleration of deep neural networks on Xilinx UltraScale MPSoCs. It is designed for maximum compute efficiency at 6-bit integer data type. It also supports 8-bit integer data type.
The design goal of CHaiDNN is to achieve best accuracy with maximum performance. The inference on CHaiDNN works in fixed point domain for better performance. All the feature maps and trained parameters are converted from single precision to fixed point based on the precision parameters specified by the user. The precision parameters can vary a lot depending upon the network, datasets, or even across layers in the same network. Accuracy of a network depends on the precision parameters used to represent the feature maps and trained parameters. Well-crafted precision parameters are expected to give accuracy similar to accuracy obtained from a single precision model.
## What's new in CHaiDNN-v2
- 4x GOPS compared to CHaiDNN-v1 (2017.4) [(Performance numbers)](./docs/PERFORMANCE_SNAPSHOT.md)
- 2x MAC on DSPs at int6
- Double-Pumped DSPs allowing the DSPs to be clocked at twice the core clock (Some configs can go upto 350/700Mhz)
- **Introducing DietChai** - A miniature version of CHai for smaller MPSoC/ Zynq devices
- 128, 256, 512, 1024 DSP design configs verified for [ZU9](https://www.xilinx.com/products/boards-and-kits/zcu102.html)
- Support for URAM
- 128, 256, 512 DSP configs verified for [ZU7](https://www.xilinx.com/products/boards-and-kits/zcu104.html)
- [ModelZoo](./docs/MODELZOO.md) of 6 networks at int8 and int6 precision
- Support for two quantization modes - [Dynamic fixed point and Xilinx Quantizer](./docs/QUANTIZATION.md)
- Enhanced API to enable better [hardware- software partitioning](./docs/HW_SW_PARTITIONING.md) for users
- Support for [software custom layer](./docs/SOFTWARE_LAYER_PLUGIN.md) plug-ins
- Fully Connected layers on CPU
- More documentation
## Performance Benchmarks(fps)
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<th>Network</th>
<th>Xilinx CHai w/ 1024DSP @ 250/500MHz (Measured on <a href="https://www.xilinx.com/products/boards-and-kits/Excerpt of 15,665 characters
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