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Top AI Repos tracks AI repositories on GitHub and answers two different questions about each one: is it moving right now, and would you bet a product on it.
Top AI Repos tracks AI repositories on GitHub and answers two different questions about each one: is it moving right now, and would you bet a product on it.
This is originally a collection of papers on neural network accelerators. Now it's more like my selection of research on deep learning and computer architecture.
| Date | Stars |
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| 2026-07-31 | 2108 |
| 2026-08-01 | 2108 |
| 2026-08-02 | 2109 |
| 2026-08-03 | 2110 |
| 2026-08-06 | 2110 |
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# Neural Networks on Silicon Fengbin Tu is an Assistant Professor and the Associate Director of the Institute of Integrated Circuits and Systems at The Hong Kong University of Science and Technology, NSFC Excellent Young Scientist, and a core faculty member of the AI Chip Center for Emerging Smart Systems (ACCESS) under InnoHK. For more informantion about Dr. Tu, please refer to [his homepage](https://fengbintu.github.io/). Dr. Tu's main research interest is AI chip and system. This is an exciting field where fresh ideas come out every day, so he's collecting works on related topics. Welcome to join! ## Table of Contents - [My Contributions](#my-contributions) - [Conference Papers](#conference-papers) - 2014: [ASPLOS](#2014-asplos), [MICRO](#2014-micro) - 2015: [ISCA](#2015-isca), [ASPLOS](#2015-asplos), [FPGA](#2015-fpga), [DAC](#2015-dac) - 2016: [ISSCC](#2016-isscc), [ISCA](#2016-isca), [MICRO](#2016-micro), [HPCA](#2016-hpca), [DAC](#2016-dac), [FPGA](#2016-fpga), [ICCAD](#2016-iccad), [DATE](#2016-date), [ASPDAC](#2016-aspdac), [VLSI](#2016-vlsi), [FPL](#2016-fpl) - 2017: [ISSCC](#2017-isscc), [ISCA](#2017-isca), [MICRO](#2017-micro), [HPCA](#2017-hpca), [ASPLOS](#2017-asplos), [DAC](#2017-dac), [FPGA](#2017-fpga), [ICCAD](#2017-iccad), [DATE](#2017-date), [VLSI](#2017-vlsi), [FCCM](#2017-fccm), [HotChips](#2017-hotchips) - 2018: [ISSCC](#2018-isscc), [ISCA](#2018-isca), [MICRO](#2018-micro), [HPCA](#2018-hpca), [ASPLOS](#2018-asplos), [DAC](#2018-dac), [FPGA](#2018-fpga), [ICCAD](#2018-iccad), [DATE](#2018-date), [ASPDAC](#2018-aspdac), [VLSI](#2018-vlsi), [HotChips](#2018-hotchips) - 2019: [ISSCC](#2019-isscc), [ISCA](#2019-isca), [MICRO](#2019-micro), [HPCA](#2019-hpca), [ASPLOS](#2019-asplos), [DAC](#2019-dac), [FPGA](#2019-fpga), [ICCAD](#2019-iccad), [ASPDAC](#2019-aspdac), [VLSI](#2019-vlsi), [HotChips](#2019-hotchips), [ASSCC](#2019-asscc) - 2020: [ISSCC](#2020-isscc), [ISCA](#2020-isca), [MICRO](#2020-micro), [HPCA](#2020-hpca), [ASPLOS](#2020-asplos), [DAC](#2020-dac), [FPGA](#2020-fpga), [ICCAD](#2020-iccad), [VLSI](#2020-vlsi), [HotChips](#2020-hotchips) - 2021: [ISSCC](#2021-isscc), [ISCA](#2021-isca), [MICRO](#2021-micro), [HPCA](#2021-hpca), [ASPLOS](#2021-asplos), [DAC](#2021-dac), [ICCAD](#2021-iccad), [VLSI](#2021-vlsi), [HotChips](#2021-hotchips) - 2022: [ISSCC](#2022-isscc), [ISCA](#2022-isca), [MICRO](#2022-micro), [HPCA](#2022-hpca), [ASPLOS](#2022-asplos), [HotChips](#2022-hotchips) - 2023: [ISSCC](#2023-isscc), [ISCA](#2023-isca), [MICRO](#2023-micro), [HPCA](#2023-hpca), [ASPLOS](#2023-asplos), [HotChips](#2023-hotchips) - 2024: [ISSCC](#2024-isscc), [ISCA](#2024-isca), [MICRO](#2024-micro), [HPCA](#2024-hpca), [ASPLOS](#2024-asplos), [HotChips](#2024-hotchips) - 2025: [ISSCC](#2025-isscc), [ISCA](#2025-isca), [MICRO](#2025-micro), [HPCA](#2025-hpca), [ASPLOS](#2025-asplos), [HotChips](#2025-hotchips) - 2026: [ISSCC](#2026-isscc), [HPCA](#2026-hpca) ## My Contributions My main research interest is AI chip and architecture. For more informantion about me and my research, you can go to [my homepage](https://fengbintu.github.io/research/). ## Conference Papers This is a collection of AI chip-related conference papers that interest me. ### 2014 ASPLOS - **DianNao: A Small-Footprint High-Throughput Accelerator for Ubiquitous Machine-Learning.** (CAS, Inria) ### 2014 MICRO - **DaDianNao: A Machine-Learning Supercomputer.** (CAS, Inria, Inner Mongolia University) ### 2015 ISCA - **ShiDianNao: Shifting Vision Processing Closer to the Sensor.** (CAS, EPFL, Inria) ### 2015 ASPLOS - **PuDianNao: A Polyvalent Machine Learning Accelerator.** (CAS, USTC, Inria) ### 2015 FPGA - **Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks.** (Peking University, UCLA) ### 2015 DAC - Reno: A Highly-Efficient Reconfigurable Neuromorphic Computing Accelerator Design. (Universtiy of Pittsburgh, Tsinghua University, San Francisco State University,
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Would you bet a product on this? Bounded 0–100 and slow moving.
matched fp:7eff3559fde37a10, topic:deep-learning