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A Convolutional Neural Network Accelerator implementation on FPGA, xilinx （xczu7ev-ffvc1156-2-i）, The inference of yolov8 took 60ms.
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https://github.com/user-attachments/assets/8335d1ec-1887-406b-8871-6fd62e5cad1e
# Open Source Accelerator on FPGA
**Read this in other languages: [english](README.md), [chinese](readme_zh.md)**
**Development Log: [english](DevLog.md), [chinese](DevLog_zh.md)**
This project aims to implement an acceleration circuit for convolutional neural networks. The project uses yolov8 as the implementation object, and the goal is to complete an acceleration circuit with operator operations such as convolution, residual sum, upsampling, pooling, and concat. Since the overall circuit design idea is efficient reusability and instructional calling, in addition to deploying the yolov8 network, other neural networks composed of the above operator operations can also be compiled onto the accelerator.
# Implementable operators
| Operators | Description |
| :-----------: | :-----------: |
| Convolution | 3*3 convolution with stride (whatever you want, int or float) and padding (Whatever). You can choose whether to activate it (dynamically controlled by parameter instructions). |
| Residual sum | Residual sum of two feature maps. |
| Upsampling | upsampling of feature maps by a factor of 2. Only support simplest nearest. |
| Pooling | pooling of feature maps with max pooling. |
| Concat | The concat is not make in circuit. It is working in the memory allocate. |
# Simulation Results
using 100Mhz clk to simulate the accelerator on yolov8n, total use 114ms.
# Working on xilinx (xczu7ev-ffvc1156-2-i)
The hardware deployment clock of the accelerator is 200Mhz, the single frame of yolov8n inference time is 60ms, and the post-processing time is 50ms. The inference and post-processing are carried out in parallel, so the total frame rate can reach 18-19FPS.
<figure class="half">
<img src="./fig/Utilization_percent.png" width="600", height="300" >
<img src="./fig/Utilization_table.png" width="600", height="300" >
</figure>
<figure>
<img src="./fig/setup.png" >
<img src="./fig/hold.png" >
<img src="./fig/pulse.png" >
</figure>
https://github.com/user-attachments/assets/aae8cbe7-0244-45a3-a5b3-8fbd66b3d928
# Quick Start
Now we have deployed two tasks on the accelerator, Yolov8 and filter.
## Environment
- modelsim
- python (include opencv, numpy)
use the following command to clone the respository:
```
git clone https://github.com/quanzaihh/Neural-Network-Accelerator
```
## Run the simulation
- Yolov8 simulation
download the yolov8n model from [yolov8n](https://pan.baidu.com/s/1zO5Mq82WNXEnz61mjo9NAw)(passcode:**d78m**) and put it in the `Neural-Network-Accelerator\compile\yolov8` folder.
Run the following command to simulate the yolov8n model:
```
cd Neural-Network-Accelerator\compile\yolov8
python Yolov8.py --Operator 0
```
- Fliter simulation (Sobel filter)
Run the following command to simulate the Sobel filter:
```
cd Neural-Network-Accelerator\compile\imageprocess
python Filter.py --Operator 0
```
## Run the hardware implementation
- Yolov8 hardware implementation
First we need to compile the model into a hardware machine code.
```
cd Neural-Network-Accelerator\compile\yolov8
python Yolov8.py --Operator 1
```
Then we will get two files in the `Neural-Network-Accelerator\compile\compile_out` folder, which is `instruction.bin` and `WeightAndBias.bin`. The `instruction.bin` file is the hardware machine code, and the `WeightAndBias.bin` file is the weight and bias of the model. The yolov8n hardware machine code is show as below:
```
REFRESH_ORDER
SET WLEN 0x011B0000
SET ORDER 0x00000001
SET FIBA 0x81000000
SET FIPN 0x00000001
SET FOPN 0x00000002
SET FDP 0x00000000
SET FPN 0x000004b0
SET ROWS 0x000001e0
SET COLS 0x00000280
SET WQS 0x00000009
SET FIQS 0x00000007
SET FExcerpt of 51,858 characters
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Would you bet a product on this? Bounded 0–100 and slow moving.
matched fp:a4c7b57dcd5e7317, llm:Repository description: 'A Convolutional Neural Network Accelerator implementation on FPGA, xilinx (xczu7ev-ffvc1156-2-i), The inference of yolov8 took 60ms.' Language: Verilog.
matched fp:a4c7b57dcd5e7317, llm:Repository description: 'A Convolutional Neural Network Accelerator implementation on FPGA, xilinx (xczu7ev-ffvc1156-2-i), The inference of yolov8 took 60ms.' Language: Verilog.
matched fp:a4c7b57dcd5e7317, llm:Repository description: 'A Convolutional Neural Network Accelerator implementation on FPGA, xilinx (xczu7ev-ffvc1156-2-i), The inference of yolov8 took 60ms.' Language: Verilog.